The development of optical fiber transmission of digital data streams has given rise to a data transfer protocol and interface system termed Fiber-Channel. Fiber-Channel technology involves coupling various computer systems together with optical fiber or a fiber-channel-compatible electrically conductive (copper) cable and allows extremely rapid data transmission speeds between machines separated by relatively great distances. A Fiber Channel family of standards (developed by the American National Standards Institute (ANSI)) defines a high speed communications interface for the transfer of large amounts of data between a variety of hardware systems such as personal computers, workstations, mainframes, supercomputers, storage devices and servers that have Fiber Channel interfaces. Use of Fiber Channel is proliferating in client/server applications that demand high bandwidth and low latency I/O. Fiber Channel achieves high performance, which is critical in opening the bandwidth limitations of current computer-to-storage and computer-to-computer interfaces at speeds up to 1 gigabit per second or faster.
Information to be transmitted over a fiber wire or cable is encoded, 8 bits at a time, into a 10-bit Transmission Character that is subsequently serially transmitted bit by bit. Data provided over a typical computer system's parallel architecture is encoded and framed such that each data byte (8-bits from the point of view of the computer system) is formed into a Transmission Character in accordance with the Fiber-Channel 8B/10B transmission code. The resulting 8B/10B character is then transmitted as 10 sequential bits at a 1.06 GHz data rate. Likewise, an incoming 8B/10B encoded transmission character must be serially received at a 1.06 GHz data rate and converted (framed) into the corresponding 10-bit transmission character. The 10-bit transmission character is then further decoded into an 8-bit byte recognizable by conventional computer architectures.
In data processing systems and data networks information is transferred over serial and parallel buses between systems, and an interface exists to provide compatibility between the data processing system and the bus to which it connects. Moreover some networks provide an interface between diverse buses with different characteristics. As an example, an interface may couple a data processing system PCI bus to a fiber channel. The PCI bus operates with parallel data paths whereas a fiber channel operates with serial data paths.
A serializer/deserializer (SERDES) forms an integral part of a fiber channel interface circuit between the serialized data paths of the fiber channel and the parallel data paths of an integrated circuit interface. A fiber channel interface connects to the SERDES through a connection and to a frame processing circuit through parallel data buses that essentially transfer information to and from the frame processing circuit.
As integrated circuits continue to increase in complexity, it is increasingly difficult to test the device. In particular, in order to test an integrated circuit, a large number of test patterns and configurations may be required. The response to the test patterns is then monitored to determine if defects are present. This testing is time-consuming and may use all of the input/output pins of the integrated circuit. Accordingly, it is known to provide a circuit(s) in the integrated circuit device itself to provide a Built-In Self Test (BIST).
Programmable logic devices (PLDs) are a well-known type of digital integrated circuit that may be programmed by a user (e.g., a circuit designer) to perform specified logic functions. One type of PLD, the field-programmable gate array (FPGA), typically includes an array of configurable logic blocks, or CLBS, that are programmably interconnected to each other and to programmable input/output blocks (IOBs). FPGAs can be provided that includes a high speed interconnect that require a SERDES.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a method of testing high speed SERDES circuitry in an FPGA.